Physical Design Course - PD
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Understanding Physical Design
What is Physical Design (PD) Role in VLSI Design Process ??
The Physical Design (PD) role is a critical step in VLSI chip development, where the logical design is transformed into a manufacturable physical layout. PD engineers ensure that the chip meets performance, power, and area (PPA) requirements while adhering to fabrication constraints. This role bridges the gap between design and silicon, making it an essential phase in the chip-making process.
Key Responsibilities of a PD Engineer
- Floorplanning and Placement : Organizing chip components for optimal area and performance.
- Clock Tree Synthesis (CTS) : Designing efficient clock distribution networks.
- Routing and Optimization : Connecting components while minimizing delays and power usage.
- Design Verification : Performing sign-off checks such as DRC, LVS, and timing analysis.
Why Choose a PD Career?
"Physical design is a high-demand career path in the semiconductor industry, offering opportunities to work on cutting-edge technologies like AI, IoT, and 5G. PD engineers play a pivotal role in delivering efficient, high-performance chips for global applications"
"Enroll in our VLSI Physical Design Training Program to gain expertise in tools like Cadence and Synopsys, master industry workflows, and work on real-world projects to launch a successful career in the semiconductor field"
Physical Design - Curriculum
1 | Introduction to VLSI
Introduction to VLSI
Topics:
- ASIC Design Flow
- ASIC vs FPGA
- ASIC RTL Design Methodologies
- ASIC Verification Methodologies
Outcome: Basic foundation over VLSI design flow and its methodologies
2 | Digital Logic Design
Advanced Digital Logic and Design
Topics:
1. Number Systems
2. Boolean Algebra
3. Logic Gates
4. Combinational Circuits
- Adder and Subtractor
- Encoder and Decoder
- Multiplexer and Demultiplexer
- Comparator
- Tri-state Buffer
5. Sequential Circuits
- Latches
- Flip-Flops
- Registers
- Counters
- Frequency Dividers
6. Finite State Machines (FSM)
- Mealy FSM
- Moore FSM
7. Memories
- SRAM & DRAM
- Composition of Memories
- FIFO
- Cache Memory
- Programmable Logic Devices (PLD)
Duration : 2-3 weeks
Outcome : Build strong fundamentals in digital logic critical for RTL design.
3 | Introduction to Physical Design
- Introduction – Overview
- Description of Physical Design Processes
- Partitioning
- Floorplan & Powerplan
- Placement
- Static Timing Analysis (Signal Integrity and Cross Talk Issues)
- Clock Tree Synthesis
- Routing
- Physical Verification & Design Sign Off
- Foundries — EcoSystem
4 | RTL Design Using Verilog HDL
RTL Design Using Verilog HDL
Topics:
1. Introduction to Verilog
- Verilog HDL language and its applications
- Basic syntax and structure (Module, Port)
- Continuous assignment (assign)
- Hierarchical design: Module instantiation and reuse
2. Data Types
- Data Type concept in RTL Design
- Net vs Reg data type
- Integer, Real,Array and String data types
3. Modeling Levels
- Gate-level modeling
- Dataflow modeling
- Behavioral modeling
4. Operators
- Arithmetic
- Relational
- Logical
- Bit wise
- Reduction
- Concatenation
- Replication
5. Basic Constructs
- Synthesizable vs. Non-synthesizable Constructs
- Procedural Blocks : Always block vs Initial block
- Sensitivity lists and edge-based triggers : always @(posedge clk) vs. always @(a or b)
- Timing Control : Blocking (=) vs. Non-blocking (<=) assignments
- Procedural Statements : if, else, case, for, while, repeat
- Compiler Directives
- System Tasks and Functions
6. Comb. and Seq. Logic Design
- Designing combinational logic (Logic Gates,Multiplexers, etc.)
- Designing sequential logic (Latches, Flip-Flops, etc.)
- Coding guidelines for RTL synthesis
- Designing Finite State Machines (FSM)
- Memory modeling (RAM, ROM)
7. Parameterized Modules
- Using parameter for reusability
- Generate blocks
Tools : Tools like ModelSim, Xilinx Vivado, or Cadence Xcelium
Duration : 2-3 weeks
Outcome : Ability to write Verilog code for basic Designs
5 | Verilog HDL Hands-on Mini-Project
Mini-Project : RTL Design and simulation of simple modules like ALU, FIFO, etc using Verilog HDL
6 | Static Timing Analysis
- Introduction to STA
- Comparison with DTA
- Timing Path and Constraints
- Different types of clocks
- Clock domain and Variations
- Clock Distribution Networks
- How to fix timing failure
- Timing Closure
- Timing ECO’s for each type of violation
- What is hierarchical timing closure – time budgeting and clocking
7 | Floor Planning
- What is FLOOR PLANNING ?
- Several criteria used to measure the quality of Floor Plans
- Inputs required
- How to qualify for Import Design?
- What is required to come with a good floor plan?
- How to do floor planning for planning Macros?
- Floor Plan Steps
- How to qualify for a Floor Plan?
- Power planning
- Analyze QOR, Timing, congestion, area, and power
- Hierarchical floor planning and design partitioning
- I/O planning and RDL routing
8 | Placement
- Introduction
- Different criteria driving the placement process
- Different tasks in placement
- Goals of placement
- Sanity checks before placement
- Placement algorithms
- Pre-placement
- Optimization techniques
- Placement qualification
- Analyze QOR, Timing, congestion, area, and power
9 | Clock Tree Synthesis
- Sanity checks need to be done before CTS Preparations
- Difference between High Fan-out Net Synthesis (HNFS) & Clock Tree Synthesis
- Concurrent Clock and Data Optimization
- What is the difference between a clock buffer and a normal buffer?
- CTS Goals
- Clock Tree Design Rule Constraints
- Clock Tree Exceptions
- NDRs
- Analyze QOR, Timing, congestion, area, and power
10 | Design Synthesis & PDKs
- Introduction to Synthesis
- Physical Synthesis
- Standard input and output files for a Synthesis tool
- How to Write SDC?
- How to analyse the synthesis report?
- LEC
- UPF
- PDK (.lib .lef .tf .ptf .rlc .ndm .dlib Milkyway, tlup files )
- Tool related Technology files
11 | Physical Verification & Sign-off
- Design Rule Check (DRC)
- Typical DRC rules
- Layout versus Schematic (LVS)
- How LVS works
- Commonly faced LVS issues
- IR Drop Analysis
- Electro Migration
- Methods to fix EM
- PERC
- Signoff
12 | Routing
- Sanity checks
- Routing flow (Global routing, Track assignment, Detailed Routing, Search and repair)
- Goals of Routing
- Routing Constraints
- Post Routing Optimization
- Analyze QOR, Timing, congestion, area, and power
13 | Soft Skills & Interview Preparation
Soft Skills & Interview Preparation
Activities:
- Resume Building and Highlighting Projects
- Mock Interviews
- Behavioural and Situational Interview Preparation
Duration: Ongoing throughout the course.
14 | Capstone Project
- Design specification analysis
- Creating the design architecture
- Partitioning the design
- RTL coding in Verilog
- RTL functional verification
- RTL Synthesis
- Place & Route the netlist
- Static Timing Analysis & ECO
- Physical Verification & Signoff
15 | Signal Integrity and Cross-Talk Issues
- Signal Integrity
- Concerns addressed by signal integrity
- Factors affecting signal integrity
- Cross-talk Noise
- Cross-talk Delay
- Antenna Effects
16 | Tcl/Tk Scripting
- Tcl overview
- Tcl vs Perl
- Evaluating TCL scripts under Unix
- TcI syntax
- Data Types
- Operators
- Branching & looping construct
- Subroutines
- File operations
- Regular expressions
- Special variables
- Built-in functions
- Introduction to Tk graphics
17 | Python Scripting
- Introduction to Python
- Python Data Types
- Numerical Data Types
- Boolean Data Types
- String Data Types
- List Data Types
- Tuple
- Dictionaries
- Set Data Types
- Python Operators
- Python Functions
- Python Conditional & loops
- Python Object Oriented Programming
- Python Exceptions
- Python File IO Operations
- Python Modules Abstraction levels
18 | CMOS Devices and Technology
- MOSFET Operation and Characteristics
- Non-ideal characteristics
- BJT vs FET
- CMOS Characteristics
- CMOS Circuit design
- Transistor sizing & Scaling
- Layout and Stick Diagrams
- CMOS Processing Steps
- IC Fabrication
- Advancements in CMOS Technology – Current Trends
19 | Basic Linux
1. Linux architecture overview
2. Basic Linux Commands
3. File System and Permissions
4. Process Management
Course Highlights
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At SEMIVLSI, we take pride in our strong partnerships with leading companies in the VLSI and semiconductor domain.These collaborations ensure that our training programs remain aligned with industry standards and provide our students with excellent placement opportunities.
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Course Name | Start Date | Timings | Training Duration | Register for Training |
Design & Verification (DV) | 03-Feb-2025 | 09:30 AM - 11:00 AM | 5 Months | |
Physical Design (PD) | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months | |
Analog Layout (AL) | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months | |
RTL Design | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months |
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Don’t wait—enroll now in SEMIVLSI and take the first step toward a successful future in the semiconductor industry.