Design Verification Course - DV
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Understanding Design Verification
What is Design Verification (DV) Role in VLSI Design Process ??
"In the VLSI industry, the Design Verification (DV) role is crucial for ensuring chip designs function flawlessly before production. DV engineers verify that a design meets its specifications by rigorously testing and debugging the functionality of digital circuits. This is a critical step in preventing costly design errors and ensuring high-quality chip performance"
Key Responsibilities of a DV Engineer :
- Testbench Development : Build environments using SystemVerilog, UVM, and other verification methodologies to automate testing processes.
- Simulation and Debugging : Run simulations to validate functionality and debug issues in hardware descriptions (HDL).
- Coverage Analysis : Ensure all design scenarios are tested, including edge cases, to achieve complete verification coverage.
- Collaboration : Work closely with design teams to resolve issues and ensure seamless design handoff.
Why Choose a DV Career?
"With the growing complexity of semiconductor designs, DV engineers are in high demand across industries like IoT, automotive, and AI. This role offers a strong career path, technical challenges, and opportunities for innovation in cutting-edge technologies"
"Join our VLSI Design Verification Training Program to gain hands-on experience in industry-standard tools, advanced methodologies, and real-world projects, preparing you for a successful career in the semiconductor industry"
Design Verification - Curriculum
1 | Introduction to VLSI
Introduction to VLSI
Topics:
- ASIC Design Flow
- ASIC vs FPGA
- ASIC RTL Design Methodologies
- ASIC Verification Methodologies
Outcome: Basic foundation over VLSI design flow and its methodologies
2 | Advanced Digital Logic and Design
Advanced Digital Logic and Design
Topics:
1. Number Systems
2. Boolean Algebra
3. Logic Gates
4. Combinational Circuits
- Adder and Subtractor
- Encoder and Decoder
- Multiplexer and Demultiplexer
- Comparator
- Tri-state Buffer
5. Sequential Circuits
- Latches
- Flip-Flops
- Registers
- Counters
- Frequency Dividers
6. Finite State Machines (FSM)
- Mealy FSM
- Moore FSM
7. Memories
- SRAM & DRAM
- Composition of Memories
- FIFO
- Cache Memory
- Programmable Logic Devices (PLD)
Duration : 2-3 weeks
Outcome : Build strong fundamentals in digital logic critical for RTL design.
3 | Introduction to Linux
Introduction to Linux
Topics:
1. Linux architecture overview
- Kernel, shell, file system hierarchy
2. Basic Linux Commands
- Basic navigation: ls, cd, pwd
- File manipulation: cat, touch, cp, mv, rm
- Viewing files: cat, less, more, head, tail
- Managing directories: mkdir, rmdir
- Help and documentation: man, –help, info
3. File System and Permissions
- Linux file system hierarchy: /home, /etc, /var, /usr, etc.
- Absolute vs. relative paths
- File Read, write, execute permissions : chmod, chown, ls -l
4. Process Management
- Foreground vs. background processes, Process states and IDs
- Process management commands: ps, top, kill, pkill
- Managing jobs: jobs, bg, fg
Duration : 1-2 weeks
Outcome : Build strong fundamentals in the Linux environment.
4 | RTL Design Using Verilog HDL
RTL Design Using Verilog HDL
Topics:
1. Introduction to Verilog
- Verilog HDL language and its applications
- Basic syntax and structure (Module, Port)
- Continuous assignment (assign)
- Hierarchical design: Module instantiation and reuse
2. Data Types
- Data Type concept in RTL Design
- Net vs Reg data type
- Integer, Real,Array and String data types
3. Modeling Levels
- Gate-level modeling
- Dataflow modeling
- Behavioral modeling
4. Operators
- Arithmetic
- Relational
- Logical
- Bit wise
- Reduction
- Concatenation
- Replication
5. Basic Constructs
- Synthesizable vs. Non-synthesizable Constructs
- Procedural Blocks : Always block vs Initial block
- Sensitivity lists and edge-based triggers : always @(posedge clk) vs. always @(a or b)
- Timing Control : Blocking (=) vs. Non-blocking (<=) assignments
- Procedural Statements : if, else, case, for, while, repeat
- Compiler Directives
- System Tasks and Functions
6. Comb. and Seq. Logic Design
- Designing combinational logic (Logic Gates,Multiplexers, etc.)
- Designing sequential logic (Latches, Flip-Flops, etc.)
- Coding guidelines for RTL synthesis
- Designing Finite State Machines (FSM)
- Memory modeling (RAM, ROM)
7. Parameterized Modules
- Using parameter for reusability
- Generate blocks
Tools : Tools like ModelSim, Xilinx Vivado, or Cadence Xcelium
Duration : 2-3 weeks
Outcome : Ability to write Verilog code for basic Designs
5 | Verilog HDL Hands-on Mini-Project
Mini-Project : RTL Design and simulation of simple modules like ALU, FIFO, etc using Verilog HDL
6 | Simulation and Debugging
Simulation and Debugging
Topics :
Simulation tools (e.g., ModelSim, XSIM, etc.)
Debugging RTL designs
Writing testbench and waveform analysis
Identifying and fixing synthesis vs simulation mismatches
Objective : Master the use of simulation tools and debugging techniques.
7 | SystemVerilog for Verification
SystemVerilog for Verification
Topics :
1. Introduction to SystemVerilog
SystemVerilog vs.Verilog: Key Differences
Need for SystemVerilog in Verification
2. Data Types
Four state & Two state data types
Struct data type
Enumerated data type
Strings
Arrays
3. Tasks and Functions in System Verilog
Differences and Applications
4. Advanced SystemVerilog Features
Interfaces: Role and Structure, Modports and Clocking Block
Classes: Basics of OOP in SystemVerilog, Constructors, Inheritance, and Polymorphism
5. Randomization
Basics of Randomization
Randomization Methods
Pre-Randomization and Post-Randomization
Constraint Randomization
Randomization Control
Randomization of Arrays
Randomization with Functions
6. Threads
Fork Join
Fork Join_any
Fork Join_none
7. InterProcessCommunication
Events
Mailboxes
Semaphores
8. Virtual Interfaces
9. Developing a Verification Environment
Writing Testbenches using SystemVerilog
Verification Planning and Testbench Architecture
Implementing Scoreboards and Coverage
Writing Directed and Constrained-Random Test Cases
Debugging with Waveforms and Logs
10. Coverage-Driven Verification
Functional Coverage: Covergroups and Coverpoints
Code Coverage: Statement, Branch, FSM, Toggle
Analyzing Coverage Reports
Techniques to Improve Coverage
Tools : Synopsys VCS, Cadence Xcelium, or equivalent tools
Duration : 2-3 weeks
Outcome : Proficiency in SystemVerilog basics for functional verification.
8 | SV Hands-on Mini-Project
Mini-Project : Verification of FIFO or UART module with random stimulus.
9 | Universal Verification Methodology (UVM)
Universal Verification Methodology (UVM)
Topics:
1. Introduction to UVM
Overview of Functional Verification
Introduction to UVM and its need in the verification process
Advantages of using UVM
Comparison with other methodologies (e.g., OVM, VMM)
2. UVM Basics
UVM Class Library Overview
UVM Testbench Architecture
Components: Driver, Monitor, Sequencer, Agent
Environment and Test
3. UVM Phases
Build, Connect, Run, and Cleanup Phases
4. UVM Factory and Object Creation
Factory Registration, Factory overrides and their importance
5. UVM Components
UVM Agents: Active vs Passive
UVM Driver: Driving transactions to the DUT
UVM Sequencer: Managing sequences and transactions
UVM Monitor: Observing and analyzing DUT outputs
UVM Scoreboard: Checking correctness and functional coverage
UVM Environment: Hierarchical composition of components
6.UVM Sequences and Transactions
Sequence Item and Transaction Classes
Writing Sequences
Sequence Arbitration
Configuring Sequences Dynamically
Randomization and Constraints
7. UVM Configuration and Reporting
UVM Configuration Database
Setting and Getting Configuration
UVM Reporting Mechanism
Message Severity Levels (INFO, WARNING, ERROR, FATAL)
Controlling verbosity and message filtering
8.UVM Advanced Topics
UVM Callbacks and TLM Interfaces
UVM Virtual Sequences and Virtual Sequencers
UVM Register Layer
Register Models and Access Mechanisms
Integration with Testbench
UVM Debugging Techniques
Debugging factory overrides
Debugging UVM phases
9. UVM Assertions and Functional Coverage
Introduction to SystemVerilog Assertions (SVA)
Integrating Assertions in UVM Testbenches
Functional Coverage
Covergroups and Coverpoints
Analyzing and Improving Coverage
Tools: UVM-compatible simulators (Questa, VCS)
Duration: 3-4 weeks
Outcome: Job-ready skills for UVM-based verification roles.
10 | UVM Hands-on Mini-Project
UVM Hands-on Mini-Project :
Building a UVM Testbench from Scratch
Verification of a Sample DUT (e.g., FIFO, ALU, or UART)
Writing Directed and Randomized Testcases
Coverage Closure and Functional Debugging
Generating Verification Reports
11 | SystemVerilog Assertions (SVA)
SystemVerilog Assertions (SVA)
1. Introduction to Assertions
- What are Assertions?
- Importance of Assertions in Verification
- Benefits of Using Assertions
- Types of Assertions Immediate Assertions Concurrent Assertions
2. Immediate Assertions
- Using assert, assume, and cover
- Examples of Immediate Assertions
- Debugging with Immediate Assertions
- Limitations of Immediate Assertions
3. Concurrent Assertions
- Basics of Temporal Logic
- Syntax and Semantics of Concurrent Assertions
- Boolean Expressions in Assertions
- Sequences and Properties
Sequence Definitions
Property Definitions - Using assert, assume, and cover with Properties
4. SVA Operators
Overview of SVA Operators
Boolean Operators
Temporal Operators (##, |->, |=>, within, throughout)
Understanding Timing Windows
Examples and Use Cases
5. Advanced SVA Concepts
- Multiple Clocks and Clock Domains
- Conditional Assertions
- Implication Operators (|-> vs. |=>)
- Repeated Events ([*], [+], [*n:m])
- Overlapping and Non-overlapping Sequences
6. Functional Coverage with Assertions
- Introduction to Functional Coverage
- Cover Properties and Cover Sequences
- Coverage Collection and Analysis
- Integrating Assertions with Coverage Goals
7. Assertion-Based Verification (ABV) Methodology
- Role of SVA in ABV
- Writing Assertions for Design Under Test (DUT)
- Assertion Planning and Strategy
- Debugging Failing Assertions
- Integrating Assertions in UVM Testbenches
8. Formal Verification with SVA
- Introduction to Formal Verification
- Using Assertions in Formal Tools
- Writing Assumptions and Constraints
- Property Checking and Debugging
- Case Studies of Formal Verification with SVA
12 | Protocol-Specific Deep Dive
Protocol-Specific Deep Dive
Topics:
- Detailed Analysis of Protocols: AMBA / PCIe / Ethernet / USB / DDR
- Verification of Protocol-Based Designs
Projects: Design and verify protocol-specific modules.
Duration: 2-3 weeks
Outcome: Familiarity with industry-relevant protocols.
13 | Soft Skills & Interview Preparation
Soft Skills & Interview Preparation
Activities:
- Resume Building and Highlighting Projects
- Mock Interviews
- Behavioural and Situational Interview Preparation
Duration: Ongoing throughout the course.
14 | Capstone Project
Capstone Project
Description: End-to-end design and verification of a project like:
- Pipelined RISC Processor
- AMBA-based Memory System
- Network Packet Processor
Tools: Integration of all learned tools and techniques.
Outcome: Comprehensive understanding of front-end VLSI workflows.
15 | RISC-V Processor
RISC-V Processor
- RISC-V Instruction Set Architecture
- RISC-V RV32I RTL Architecture Design
- RISC-V RV32I 5 stage Pipelined RTL Design
Course Highlights
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Course Name | Start Date | Timings | Training Duration | Register for Training |
Design & Verification (DV) | 03-Feb-2025 | 09:30 AM - 11:00 AM | 5 Months | |
Physical Design (PD) | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months | |
Analog Layout (AL) | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months | |
RTL Design | 03-Mar-2025 | 09:30 AM - 11:00 AM | 5 Months |
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Don’t wait—enroll now in SEMIVLSI and take the first step toward a successful future in the semiconductor industry.